The level of integration within integrated circuits (ICs) has led to larger numbers of IC interconnections as well as higher data rates. Today, typical signal speed of ICs is approximately 3 GHz, and shortly it will reach 10 GHz and higher. The number of interconnections required in a single IC (e.g., a single processor) may be close to 2000, and shortly that number will increase to over 5000. Simultaneously achieving higher data rates and higher numbers of on-chip, and off-chip interconnection densities (number of interconnections per unit area) is becoming increasingly difficult as IC technologies continue to evolve. For example, in on-chip cases, as the number of electronic devices such as transistors, are increased, interconnecting the electronic devices without sacrificing the signal speed is more and more challenging. Similarly, in off-chip cases, high density of interconnections, including die-level and chip-to-chip packaging (hereafter “chip” indicates the die with package) on the printed circuit board (PCB), will also be increasingly difficult.
Therefore, increasing the signal speed and number of interconnections within, and outside the ICs by using a low-cost, high-level interconnection technique compatible with existing manufacturing processes, is highly desirable.
It is generally known in the art that at signal speeds below a few Megahertz (MHz), electronic devices (both on-chip and off-chip) are interconnected using a metal conductor for example, a metal wire, for electrical signals to flow. However for speeds higher than a few MHz, both on-chip and off-chip signals must propagate through impedance matched transmission lines. Any discontinuities in the electrical signal line or via holes (conducting pathways between two or more substrates/layers) due to impedance mismatch causes reflection thereby degrading the signal waveform propagating through the electronic devices. At multi GHz frequencies, the transmission line loss which is the sum of the conductor loss and the dielectric loss are dependent on the transmission frequency. Significant attenuation and rise-time degradation can be caused by losses in the transmission line. Furthermore, interconnection lengths become a significant fraction of the wavelength of the high frequency harmonics. Therefore, interconnections must be designed with proper concern for impedance, cross talk, and attenuation. Impedance mismatch must be minimized to reduce the reflections and prevent ringing, which can cause a false decision (switching) in the receiver.
At present, technology development is pushing towards a reduction in the size of the electronic device, resulting in utilization of a larger number of devices inside a single chip. As the level of integration of future ‘system-on-a-chip’ design is increasing, chip areas are also increasing. There is high demand for a novel interconnection technique that is compatible with standard IC fabrication technology, while preserving the signal speed, and assuring adequate isolation for high-speed data communication. As the on-chip signal speed increases, the off-chip signal speed also increases, thereby requiring new techniques for off-chip interconnections that are compatible with the current PCB technology.
FIG. 1 and FIG. 2 are schematics that show parts of conventional on-chip and off-chip interconnections. In particular, an on-chip interconnection shown in FIG. 1, comprises a single substrate 100 including an electronic device 102 connected by metal conductors 104. The metal conductors are typically made of materials including aluminum (Al), copper (Cu), tungsten (W), and tungsten silicide (WSi). One or more dielectric layers 106 comprising for example silicon oxide (for a Si devices), isolate the device from other metal conductors and from other devices (not shown here).
A schematic of an off-chip interconnection is shown in FIG. 2, wherein a chip 120 (for example, a CPU processor) is connected to another chip 130 on a PCB 108, by multilayered electrical signal lines 110. FIG. 3 and FIG. 4 respectively, show a schematic representation of a conventional BGA (ball grid array) and a CSP (chip-scaled package) packaging for a high-speed single chip package (for example, a processor). In both types of packaging, a die 122 (FIG. 3) or a die 132 (FIG. 4) are attached to a ceramic or a polymer substrate 134 (FIG. 4), respectively, containing the matrix of pins 126 (FIG. 3) and 136 (FIG. 4). Outside pins 128 (FIG. 3) and 138 (FIG. 4), located at the bottom-side of the chip package (not shown in both packaging cases), connect with the PCB 108. Heat sinks are attached to the top side of the dies to dissipate heat from the dies. The signal fidelity occurs due to the conventional inter-chip electrical signal connections 110 and ground/power 112 connections through the multilayered PCB 108. It is highly desirable to have board-level electrical interconnections for high-speed inter-chip connection, which are compatible with existing IC packages such as BGA, CSP, etc., as well as conventional PCB technologies.
Interconnection technology for both on-chip (intra-chip) and off-chip (inter-chip) interconnections is mainly based on a microstrip line type or a strip-line type transmission line layout laid on a dielectric material. FIG. 5A shows a cross-sectional view of a microstrip line type transmission line layout having a trace routed for example at a top or a bottom layer of a PCB, in an off-chip interconnection. An electrical conductor 140A to be referred as a “signal” line hereinafter, with a width W and a thickness T is laid on a dielectric material 142A having height H. A ground and/or a power line 144A is located on the bottom side of the PCB, opposite from the signal line 140A. FIG. 5B is the cross-sectional view of a strip-line type transmission line layout, which has a trace 140B routed on the inside of the PCB layer 142B and has two voltage-reference planes (i.e. power and/or ground) 144B and 144B′. The impedances of the microstrip line type and the strip-line type transmission lines are expressed by the following equations, respectively:Zmicrostrip=[(87/Sqrt.(εr+1.41)]ln[(5.98×H)/(0.8W+T)]Ω  (1)Zstrip=[(60/Sqrt.(εr))]]]ln[(4 H)/(0.67π(0.8W+T))]]]Ω  (2)
Equations (1) and (2) indicate that the impedance is directly proportional to the dielectric constant εr and the trace height H, and is inversely proportional to the trace width W and the trace thickness T. In a strip-line layout, the signal line is confined within the dielectric layer, whereas in a microstrip line layout the signal line is open to air. In a microstrip line type trace, the electrical field is in the dielectric layer as well as in the air, whereas in a strip-line type trace, the field is confined inside the dielectric layer. Hence, the effective dielectric constant in the strip-line layout is higher as compared to in the microstrip line layout. There is also less dielectric loss (also referred as dielectric loss tangent) in the microstrip line layouts as compared to the strip-line layout. The higher effective dielectric loss in the strip-line layout results in higher dispersion or signal loss as compared to the microstrip line layout. FIG. 6 in a top view and a cross-sectional view of a microstrip line type transmission line layout shows the electrical field distribution. The electrical field 146A spreads to both sides of the signal line 140A. FIG. 7A and FIG. 7B show frequency responses of microstrip line and strip-line layouts. For the same dielectric material, the effective dielectric constant of the strip-line layout is higher than that of the microstrip line layout. The signal is attenuated more in the strip-line layout at higher frequencies. Therefore, to increase the bandwidth of the interconnection, the effective dielectric loss should be kept low.
A high-speed signal while propagating through the transmission line, experiences a propagation delay which is dependent on the dielectric constant of the material. The propagation delay tPD for strip line and microstrip line type transmission lines are expressed by the following equations, respectively:tPD microstrip=85 [Sqrt.(0.475εr+0.67)]  (3)tPD stripline=85 [Sqrt.(εr)]  (4)
Equations (3) and (4) indicate that as εr increases, the propagation delay also increases. A microstrip line layout has comparatively lower propagation delay than a strip line layout for the fixed dielectric constant εr.
A signal experiences more propagation delay in a transmission line laid on a dielectric medium having a high dielectric constant compared to a dielectric medium having a low dielectric constant. This causes signal skews for different length signal lines. Therefore, a lower-dielectric constant medium is preferred in constructing on-chip and off-chip high-speed signal interconnections. A dielectric medium having a low dielectric constant and a low dielectric loss tangent offer the following advantages:
(1) A reduction in cross-talk allows higher on-chip and off-chip interconnection density,
(2) a reduction in interconnection capacitance allows signal propagation over longer distances,
(3) a lower propagation delay, and
(4) a reduction in microwave loss due to confinement of the electric field near the signal line, which helps signal propagation over longer distances. Therefore, it is advantageous to transmit high speed signals in a medium having a low dielectric constant as compared to a medium having a high dielectric constant with substantially the same dielectric loss tangent.
Besides the dielectric constant of the medium, the type of signal line, the microwave loss, and the material used for conductor electrode structure also limits the bandwidth of an interconnection. Microwave-loss occurs due to the electrode structure material, mainly as a result of the skin-depth of the signal. As skin-depth of copper at 100 GHz is about 0.2 μm, therefore loss due to the skin-depth in a copper conductor electrode may be neglected. In that case, the bandwidth of the interconnection (on-chip and off-chip) is mainly dependent on the following factors:
(1) length of the interconnection;
(2) microwave-loss, originating from, (a) dielectric constant, (b) dielectric loss tangent, and (c) electrode structure material. As the length of the interconnection in on-chip and off-chip applications varies from a few micrometers to about 10 to 30 cm, the dependence on interconnection length can be neglected. Therefore, the interconnection bandwidth is mainly dependent on the dielectric constant and the dielectric loss tangent.
Those skilled in the art will appreciate that it is preferable to use a material having a low dielectric constant as well as a lower dielectric loss tangent. Therefore, it is necessary to develop new materials, and new manufacturing technology for constructing on-chip and off-chip interconnections.
Currently, a lot of work is focused on developing new materials for on-chip and off-chip interconnection technology. For example, for on-chip interconnection, it is possible to find low-K materials having a dielectric constant between 3.0 and 4.5, which is lower than the dielectric constant of non-doped silicon oxide. However, beyond that, it will be necessary to find other materials. In addition, incorporating new materials in the chip fabrication process is expensive in short term until the technology matures. At present, developing low-K materials for on-chip interconnection is expensive and time consuming. On the other hand, for off-chip interconnection, and especially for chip-to-chip interconnection, efforts are focused on shortening the length of the interconnection and/or the interconnection layout. In both cases, IC manufacturing costs would increase in implementing new technology.
With growing demand on higher signal speeds and larger bandwidth interconnections, the conventional technology currently being used for on-chip and off-chip interconnection cannot be continued without incurring higher cost. It is desirable and even cost effective to adopt new materials having a lower dielectric constant and lower dielectric loss tangent and manufacturing methods that are compatible with current IC and PCB manufacturing technology.